Update module 'memory' to run on atmega1284p hardware

This commit is contained in:
2024-09-30 19:46:38 +02:00
parent 595b30cbe5
commit 68050b6226

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@@ -189,14 +189,14 @@ static void ReadBlock(int n, mem_block_t *out)
static void WriteRaw(int addr, byte data) static void WriteRaw(int addr, byte data)
{ {
// The EEMWE bit determines whether setting EEWE to // The EEMPE bit determines whether setting EEPE to
// one causes the EEPROM to be written. When EEMWE // one causes the EEPROM to be written. When EEMPE
// is set, setting EEWE within four clock cycles // is set, setting EEPE within four clock cycles
// will write data to the EEPROM at the selected // will write data to the EEPROM at the selected
// address. // address.
// If EEMWE is zero, setting EEWE will have no // If EEMPE is zero, setting EEPE will have no
// effect. When EEMWE has been written to one by // effect. When EEMPE has been written to one by
// software, hardware clears the bit to zero after // software, hardware clears the bit to zero after
// four clock cycles. // four clock cycles.
@@ -206,33 +206,40 @@ static void WriteRaw(int addr, byte data)
// If an interrupt routine accessing the EEPROM is // If an interrupt routine accessing the EEPROM is
// interrupting another EEPROM Access, the EEAR or // interrupting another EEPROM Access, the EEAR or
// EEDR reGister will be modified, causing the // EEDR register will be modified, causing the
// interrupted EEPROM Access to fail. // interrupted EEPROM Access to fail.
// It is recommended to have the Global Interrupt // It is recommended to have the Global Interrupt
// Flag cleared during all the steps to avoid these // Flag cleared during all the steps to avoid these
// problems. // problems.
// When the write access time has elapsed, the EEPE
// bit is cleared by hardware. The user software can
// poll this bit and wait for a zero before writing
// the next byte. When EEPE has been set, the CPU is
// halted for two cycles before the next instruction
// is executed.
// No interrupts during EEPROM write // No interrupts during EEPROM write
ATOMIC_BLOCK(ATOMIC_RESTORESTATE) { ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
// Wait until ready // Wait until ready
while (EECR & BIT(EEWE)); while (EECR & BIT(EEPE));
// The EEPROM Address Registers EEARH and // The EEPROM Address Registers EEARH and
// EEARL specify the EEPROM address in the // EEARL specify the EEPROM address in the
// 1024bytes EEPROM space. The EEPROM data // 512/1K/2K/4Kbytes EEPROM space. The EEPROM
// bytes are addressed linearly between 0 // data bytes are addressed linearly between 0
// and 1023. The initial value of EEAR is // and 511/1023/2047/4096. The initial value
// undefined. A proper value must be written // of EEAR is undefined. A proper value must be
// before the EEPROM may be accessed. // written before the EEPROM may be accessed.
EEAR = addr; EEAR = addr;
EEDR = data; EEDR = data;
// Write to address // Write to address
EECR |= BIT(EEMWE); EECR |= BIT(EEMPE);
EECR |= BIT(EEWE); EECR |= BIT(EEPE);
} }
} }
@@ -256,7 +263,7 @@ static byte ReadRaw(int addr)
ATOMIC_BLOCK(ATOMIC_RESTORESTATE) { ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
// Wait until ready // Wait until ready
while (EECR & BIT(EEWE)); while (EECR & BIT(EEPE));
EEAR = addr; EEAR = addr;