From 68050b62264f0f3cee51ce257b7edddc695a03d0 Mon Sep 17 00:00:00 2001
From: Leon Krieg <info@madcow.dev>
Date: Mon, 30 Sep 2024 19:46:38 +0200
Subject: [PATCH] Update module 'memory' to run on atmega1284p hardware

---
 src/common/memory.c | 39 +++++++++++++++++++++++----------------
 1 file changed, 23 insertions(+), 16 deletions(-)

diff --git a/src/common/memory.c b/src/common/memory.c
index a691c1a..8680081 100644
--- a/src/common/memory.c
+++ b/src/common/memory.c
@@ -189,14 +189,14 @@ static void ReadBlock(int n, mem_block_t *out)
 
 static void WriteRaw(int addr, byte data)
 {
-	// The EEMWE bit determines whether setting EEWE to
-	// one causes the EEPROM to be written. When EEMWE
-	// is set, setting EEWE within four clock cycles
+	// The EEMPE bit determines whether setting EEPE to
+	// one causes the EEPROM to be written. When EEMPE
+	// is set, setting EEPE within four clock cycles
 	// will write data to the EEPROM at the selected
 	// address.
 
-	// If EEMWE is zero, setting EEWE will have no
-	// effect. When EEMWE has been written to one by
+	// If EEMPE is zero, setting EEPE will have no
+	// effect. When EEMPE has been written to one by
 	// software, hardware clears the bit to zero after
 	// four clock cycles.
 
@@ -206,33 +206,40 @@ static void WriteRaw(int addr, byte data)
 
 	// If an interrupt routine accessing the EEPROM is
 	// interrupting another EEPROM Access, the EEAR or
-	// EEDR reGister will be modified, causing the
+	// EEDR register will be modified, causing the
 	// interrupted EEPROM Access to fail.
 
 	// It is recommended to have the Global Interrupt
 	// Flag cleared during all the steps to avoid these
 	// problems.
 
+	// When the write access time has elapsed, the EEPE
+	// bit is cleared by hardware. The user software can
+	// poll this bit and wait for a zero before writing
+	// the next byte. When EEPE has been set, the CPU is
+	// halted for two cycles before the next instruction
+	// is executed.
+
 	// No interrupts during EEPROM write
 	ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
 
 		// Wait until ready
-		while (EECR & BIT(EEWE));
+		while (EECR & BIT(EEPE));
 
 		// The EEPROM Address Registers – EEARH and
-		// EEARL – specify the EEPROM address in the
-		// 1024bytes EEPROM space. The EEPROM data
-		// bytes are addressed linearly between 0
-		// and 1023. The initial value of EEAR is
-		// undefined. A proper value must be written
-		// before the EEPROM may be accessed.
+		// EEARL specify the EEPROM address in the
+		// 512/1K/2K/4Kbytes EEPROM space. The EEPROM
+		// data bytes are addressed linearly between 0
+		// and 511/1023/2047/4096. The initial value
+		// of EEAR is undefined. A proper value must be
+		// written before the EEPROM may be accessed.
 
 		EEAR = addr;
 		EEDR = data;
 
 		// Write to address
-		EECR |= BIT(EEMWE);
-		EECR |= BIT(EEWE);
+		EECR |= BIT(EEMPE);
+		EECR |= BIT(EEPE);
 	}
 }
 
@@ -256,7 +263,7 @@ static byte ReadRaw(int addr)
 	ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
 
 		// Wait until ready
-		while (EECR & BIT(EEWE));
+		while (EECR & BIT(EEPE));
 
 		EEAR = addr;