Update module 'memory' to run on atmega1284p hardware
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@@ -189,14 +189,14 @@ static void ReadBlock(int n, mem_block_t *out)
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static void WriteRaw(int addr, byte data)
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static void WriteRaw(int addr, byte data)
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{
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{
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// The EEMWE bit determines whether setting EEWE to
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// The EEMPE bit determines whether setting EEPE to
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// one causes the EEPROM to be written. When EEMWE
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// one causes the EEPROM to be written. When EEMPE
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// is set, setting EEWE within four clock cycles
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// is set, setting EEPE within four clock cycles
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// will write data to the EEPROM at the selected
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// will write data to the EEPROM at the selected
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// address.
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// address.
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// If EEMWE is zero, setting EEWE will have no
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// If EEMPE is zero, setting EEPE will have no
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// effect. When EEMWE has been written to one by
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// effect. When EEMPE has been written to one by
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// software, hardware clears the bit to zero after
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// software, hardware clears the bit to zero after
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// four clock cycles.
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// four clock cycles.
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@@ -206,33 +206,40 @@ static void WriteRaw(int addr, byte data)
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// If an interrupt routine accessing the EEPROM is
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// If an interrupt routine accessing the EEPROM is
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// interrupting another EEPROM Access, the EEAR or
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// interrupting another EEPROM Access, the EEAR or
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// EEDR reGister will be modified, causing the
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// EEDR register will be modified, causing the
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// interrupted EEPROM Access to fail.
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// interrupted EEPROM Access to fail.
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// It is recommended to have the Global Interrupt
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// It is recommended to have the Global Interrupt
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// Flag cleared during all the steps to avoid these
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// Flag cleared during all the steps to avoid these
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// problems.
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// problems.
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// When the write access time has elapsed, the EEPE
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// bit is cleared by hardware. The user software can
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// poll this bit and wait for a zero before writing
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// the next byte. When EEPE has been set, the CPU is
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// halted for two cycles before the next instruction
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// is executed.
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// No interrupts during EEPROM write
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// No interrupts during EEPROM write
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ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
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ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
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// Wait until ready
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// Wait until ready
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while (EECR & BIT(EEWE));
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while (EECR & BIT(EEPE));
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// The EEPROM Address Registers – EEARH and
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// The EEPROM Address Registers – EEARH and
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// EEARL – specify the EEPROM address in the
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// EEARL specify the EEPROM address in the
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// 1024bytes EEPROM space. The EEPROM data
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// 512/1K/2K/4Kbytes EEPROM space. The EEPROM
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// bytes are addressed linearly between 0
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// data bytes are addressed linearly between 0
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// and 1023. The initial value of EEAR is
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// and 511/1023/2047/4096. The initial value
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// undefined. A proper value must be written
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// of EEAR is undefined. A proper value must be
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// before the EEPROM may be accessed.
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// written before the EEPROM may be accessed.
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EEAR = addr;
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EEAR = addr;
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EEDR = data;
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EEDR = data;
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// Write to address
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// Write to address
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EECR |= BIT(EEMWE);
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EECR |= BIT(EEMPE);
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EECR |= BIT(EEWE);
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EECR |= BIT(EEPE);
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}
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}
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}
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}
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@@ -256,7 +263,7 @@ static byte ReadRaw(int addr)
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ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
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ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
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// Wait until ready
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// Wait until ready
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while (EECR & BIT(EEWE));
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while (EECR & BIT(EEPE));
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EEAR = addr;
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EEAR = addr;
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