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282
backends/platform/ds/blitters_arm.s
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282
backends/platform/ds/blitters_arm.s
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@ ScummVM - Graphic Adventure Engine
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@
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@ ScummVM is the legal property of its developers, whose names
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@ are too numerous to list here. Please refer to the COPYRIGHT
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@ file distributed with this source distribution.
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@
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@ This program is free software: you can redistribute it and/or modify
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@ it under the terms of the GNU General Public License as published by
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@ the Free Software Foundation, either version 3 of the License, or
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@ (at your option) any later version.
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@
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@ This program is distributed in the hope that it will be useful,
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@ but WITHOUT ANY WARRANTY; without even the implied warranty of
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@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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@ GNU General Public License for more details.
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@
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@ You should have received a copy of the GNU General Public License
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@ along with this program. If not, see <http://www.gnu.org/licenses/>.
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@
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@ @author Robin Watts (robin@wss.co.uk)
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.global Rescale_320x256xPAL8_To_256x256x1555
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.global Rescale_320x256x1555_To_256x256x1555
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@ .section .itcm,"ax", %progbits
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.align 2
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.code 32
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@ ARM implementation of Rescale_320x256x1555_To_256x256x1555
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@
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@ C prototype would be:
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@
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@ extern "C" void Rescale_320x256x1555_To_256x256x1555(
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@ u16 *dst,
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@ const u16 *src,
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@ int dstStride,
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@ int srcStride);
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Rescale_320x256x1555_To_256x256x1555:
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@ r0 = dst
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@ r1 = src
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@ r2 = dstStride
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@ r3 = srcStride
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STMFD r13!,{r4-r6,r8-r11,r14}
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SUB r2,r2,#64*4 @ srcStride -= line length
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SUB r3,r3,#64*5 @ dstStride -= line length
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MOV r8, #0x0000001F
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ORR r8, r8,#0x00007C00
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ORR r8, r8,#0x03E00000 @ r8 = mask
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MOV r6, #0x8000
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ORR r6, r6, r6, LSL #16
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MOV r5, #200 @ r5 = y
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yLoop3:
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MOV r4, #64 @ r4 = x
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xLoop3:
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LDRH r9, [r1],#2 @ r9 = src0
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LDRH r10,[r1],#2 @ r10= src1
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LDRH r11,[r1],#2 @ r11= src2
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LDRH r12,[r1],#2 @ r12= src3
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LDRH r14,[r1],#2 @ r14= src4
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ORR r9, r9, r9, LSL #16 @ r9 = src0 | src0
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ORR r10,r10,r10,LSL #16 @ r10= src1 | src1
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ORR r11,r11,r11,LSL #16 @ r11= src2 | src2
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ORR r12,r12,r12,LSL #16 @ r12= src3 | src3
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ORR r14,r14,r14,LSL #16 @ r13= src4 | src4
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AND r9, r9, r8 @ r9 = 0 | G0 | 0 | B0 | 0 | R0
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AND r10,r10,r8 @ r10= 0 | G1 | 0 | B1 | 0 | R1
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AND r11,r11,r8 @ r11= 0 | G2 | 0 | B2 | 0 | R2
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AND r12,r12,r8 @ r12= 0 | G3 | 0 | B3 | 0 | R3
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AND r14,r14,r8 @ r14= 0 | G4 | 0 | B4 | 0 | R4
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ADD r9, r9, r9, LSL #1 @ r9 = 3*src0
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ADD r9, r9, r10 @ r9 = dst0<<2
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ADD r10,r10,r11 @ r10= dst1
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ADD r11,r11,r12 @ r11= dst2
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ADD r12,r12,r14 @ r12= src3 + src4
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ADD r12,r12,r14,LSL #1 @ r12= src3 + src4*3 = dst3<<2
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AND r9, r8, r9, LSR #2 @ r9 = dst0 (split)
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AND r10,r8, r10,LSR #1 @ r10= dst1 (split)
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AND r11,r8, r11,LSR #1 @ r11= dst2 (split)
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AND r12,r8, r12,LSR #2 @ r12= dst3 (split)
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ORR r9, r9, r9, ROR #16 @ r9 = dst0
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ORR r10,r10,r10,ROR #16 @ r10= dst1
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ORR r11,r11,r11,ROR #16 @ r11= dst2
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ORR r12,r12,r12,ROR #16 @ r12= dst3
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ORR r10,r6, r10,LSL #16
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ORR r9, r10,r9, LSR #16
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ORR r12,r6, r12,LSL #16
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ORR r11,r12,r11,LSR #16
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STMIA r0!,{r9,r11}
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SUBS r4,r4,#1
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BGT xLoop3
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ADD r0,r0,r2,LSL #1
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ADD r1,r1,r3,LSL #1
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SUBS r5,r5,#1
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BGT yLoop3
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LDMFD r13!,{r4-r6,r8-r11,PC}
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@ ARM implementation of Rescale_320x256xPAL8_To_256x256x1555
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@
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@ C prototype would be:
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@
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@ extern "C" void Rescale_320x256xPAL8_To_256x256x1555(
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@ u16 *dst,
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@ const u8 *src,
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@ int dstStride,
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@ int srcStride,
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@ const u16 *pal,
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@ u32 numLines);
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Rescale_320x256xPAL8_To_256x256x1555:
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@ r0 = dst
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@ r1 = src
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@ r2 = dstStride
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@ r3 = srcStride
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STMFD r13!,{r4-r11,r14}
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MOV r8, #0x0000001F
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ORR r8, r8,#0x0000FC00
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ORR r8, r8,#0x03E00000 @ r8 = mask
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LDR r9, [r13,#9*4] @ r9 = palette
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LDR r7, [r13,#10*4] @ r7 = numLines
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SUB r13,r13,#256*4 @ r13 = 1K of space on the stack.
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MOV r5, r13 @ r5 points to this space
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MOV r14,#256
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palLoop:
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LDRH r10,[r9],#2 @ r10 = palette entry
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SUBS r14,r14,#1
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ORR r10,r10,r10,LSL #16
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AND r10,r10,r8 @ r10 = separated palette entry
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ORR r10,r10,#0x00008000
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STR r10,[r5], #4
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BGT palLoop
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SUB r2,r2,#64*4 @ srcStride -= line length
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SUB r3,r3,#64*5 @ dstStride -= line length
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MOV r14,#0xFF @ r14= 255
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MOV r5,r7 @ r5 = numLines
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yLoop4:
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MOV r4,#16 @ r4 = x
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xLoop4:
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LDMIA r1!,{r10,r11,r12}
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AND r6, r14,r10 @ r6 = src0
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LDR r6, [r13,r6, LSL #2] @ r6 = pal[src0]
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AND r7, r14,r10,LSR #8 @ r7 = src1
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LDR r7, [r13,r7, LSL #2] @ r7 = pal[src1]
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ADD r6, r6, r6, LSL #1 @ r6 = 3*pal[src0]
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AND r9, r14,r10,LSR #16 @ r9 = src2
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LDR r9, [r13,r9, LSL #2] @ r9 = pal[src2]
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MOV r10,r10,LSR #24 @ r10= src3
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LDR r10,[r13,r10,LSL #2] @ r10= pal[src3]
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ADD r6, r6, r7 @ r6 = dst0<<2
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AND r6, r8, r6, LSR #2 @ r6 = dst0 (split)
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ORR r6, r6, r6, ROR #16 @ r6 = dst0 (in both halves)
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ADD r7, r7, r9 @ r7 = dst1<<1
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AND r7, r8, r7, LSR #1 @ r7 = dst1 (split)
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ORR r7, r7, r7, ROR #16 @ r7 = dst1 (in both halves)
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MOV r7, r7, LSL #16 @ r7 = dst1<<16
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ORR r6, r7, r6, LSR #16 @ r6 = dst0 | dst1<<16
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AND r7, r14,r11 @ r7 = src4
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LDR r7, [r13,r7, LSL #2] @ r7 = pal[src4]
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ADD r9, r9, r10 @ r9 = dst2<<1
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AND r9, r8, r9, LSR #1 @ r9 = dst2 (split)
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ORR r9, r9, r9, ROR #16 @ r9 = dst2 (in both halves)
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ADD r10,r10,r7 @ r7 = pal[src3]+pal[src4]
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ADD r10,r10,r7, LSL #1 @ r10= dst3<<2
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AND r10,r8, r10,LSR #2 @ r10= dst3 (split)
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ORR r10,r10,r10,ROR #16 @ r10= dst3 (in both halves)
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MOV r7, r9, LSR #16
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ORR r7, r7, r10, LSL #16 @ r7 = dst2 | dst3<<16
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STMIA r0!,{r6,r7}
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AND r6, r14,r11,LSR #8 @ r6 = src5
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LDR r6, [r13,r6, LSL #2] @ r6 = pal[src5]
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AND r7, r14,r11,LSR #16 @ r7 = src6
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LDR r7, [r13,r7, LSL #2] @ r7 = pal[src6]
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ADD r6, r6, r6, LSL #1 @ r6 = 3*pal[src5]
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MOV r9, r11,LSR #24 @ r9 = src7
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LDR r9, [r13,r9, LSL #2] @ r9 = pal[src7]
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AND r10,r14,r12 @ r10= src8
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LDR r10,[r13,r10,LSL #2] @ r10= pal[src8]
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ADD r6, r6, r7 @ r6 = dst4<<2
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AND r6, r8, r6, LSR #2 @ r6 = dst4 (split)
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ORR r6, r6, r6, ROR #16 @ r6 = dst4 (in both halves)
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ADD r7, r7, r9 @ r7 = dst5<<1
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AND r7, r8, r7, LSR #1 @ r7 = dst5 (split)
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ORR r7, r7, r7, ROR #16 @ r7 = dst5 (in both halves)
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MOV r7, r7, LSL #16 @ r7 = dst5<<16
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ORR r6, r7, r6, LSR #16 @ r6 = dst4 | dst5<<16
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AND r7, r14,r12,LSR #8 @ r7 = src9
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LDR r7, [r13,r7, LSL #2] @ r7 = pal[src9]
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ADD r9, r9, r10 @ r9 = dst6<<1
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AND r9, r8, r9, LSR #1 @ r9 = dst6 (split)
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ORR r9, r9, r9, ROR #16 @ r9 = dst6 (in both halves)
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ADD r10,r10,r7 @ r10= pal[src8]+pal[src9]
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ADD r10,r10,r7, LSL #1 @ r10= dst7<<2
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AND r10,r8, r10,LSR #2 @ r10= dst7 (split)
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ORR r10,r10,r10,ROR #16 @ r10= dst7 (in both halves)
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MOV r7, r9, LSR #16
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ORR r7, r7, r10, LSL #16 @ r7 = dst6 | dst7<<16
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LDMIA r1!,{r10,r11}
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SUBS r4,r4,#1
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STMIA r0!,{r6,r7}
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AND r6, r14,r12,LSR #16 @ r6 = src10
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LDR r6, [r13,r6, LSL #2] @ r6 = pal[src10]
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MOV r7, r12,LSR #24 @ r7 = src11
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LDR r7, [r13,r7, LSL #2] @ r7 = pal[src11]
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ADD r6, r6, r6, LSL #1 @ r6 = 3*pal[src10]
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AND r9, r14,r10 @ r9 = src12
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LDR r9, [r13,r9, LSL #2] @ r9 = pal[src12]
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AND r12,r14,r10,LSR #8 @ r11= src13
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LDR r12,[r13,r12,LSL #2] @ r11= pal[src13]
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ADD r6, r6, r7 @ r6 = dst8<<2
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AND r6, r8, r6, LSR #2 @ r6 = dst8 (split)
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ORR r6, r6, r6, ROR #16 @ r6 = dst8 (in both halves)
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ADD r7, r7, r9 @ r7 = dst9<<1
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AND r7, r8, r7, LSR #1 @ r7 = dst9 (split)
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ORR r7, r7, r7, ROR #16 @ r7 = dst9 (in both halves)
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MOV r7, r7, LSL #16 @ r7 = dst9<<16
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ORR r6, r7, r6, LSR #16 @ r6 = dst8 | dst9<<16
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AND r7, r14,r10,LSR #16 @ r7 = src14
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LDR r7, [r13,r7, LSL #2] @ r7 = pal[src14]
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ADD r9, r9, r12 @ r9 = dst10<<1
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AND r9, r8, r9, LSR #1 @ r9 = dst10 (split)
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ORR r9, r9, r9, ROR #16 @ r9 = dst10 (in both halves)
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ADD r12,r12,r7 @ r12= pal[src13]+pal[src14]
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ADD r12,r12,r7, LSL #1 @ r12= dst11<<2
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AND r12,r8, r12,LSR #2 @ r12= dst11 (split)
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ORR r12,r12,r12,ROR #16 @ r12= dst11 (in both halves)
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MOV r7, r9, LSR #16
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ORR r7, r7, r12, LSL #16 @ r7 = dst10 | dst11<<16
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STMIA r0!,{r6,r7}
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MOV r6, r10,LSR #24 @ r6 = src15
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LDR r6, [r13,r6, LSL #2] @ r6 = pal[src15]
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AND r7, r14,r11 @ r7 = src16
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LDR r7, [r13,r7, LSL #2] @ r7 = pal[src16]
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ADD r6, r6, r6, LSL #1 @ r6 = 3*pal[src15]
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AND r9, r14,r11,LSR #8 @ r9 = src17
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LDR r9, [r13,r9, LSL #2] @ r9 = pal[src17]
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AND r12,r14,r11,LSR #16 @ r11= src18
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LDR r12,[r13,r12,LSL #2] @ r11= pal[src18]
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ADD r6, r6, r7 @ r6 = dst12<<2
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AND r6, r8, r6, LSR #2 @ r6 = dst12 (split)
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ORR r6, r6, r6, ROR #16 @ r6 = dst12 (in both halves)
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ADD r7, r7, r9 @ r7 = dst13<<1
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AND r7, r8, r7, LSR #1 @ r7 = dst13 (split)
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ORR r7, r7, r7, ROR #16 @ r7 = dst13 (in both halves)
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MOV r7, r7, LSL #16 @ r7 = dst13<<16
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ORR r6, r7, r6, LSR #16 @ r6 = dst12 | dst13<<16
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MOV r7, r11,LSR #24 @ r7 = src19
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LDR r7, [r13,r7, LSL #2] @ r7 = pal[src19]
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ADD r9, r9, r12 @ r9 = dst14<<1
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AND r9, r8, r9, LSR #1 @ r9 = dst14 (split)
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ORR r9, r9, r9, ROR #16 @ r9 = dst14 (in both halves)
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ADD r12,r12,r7 @ r12= pal[src18]+pal[src19]
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ADD r12,r12,r7, LSL #1 @ r12= dst15<<2
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AND r12,r8, r12,LSR #2 @ r12= dst15 (split)
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ORR r12,r12,r12,ROR #16 @ r12= dst15 (in both halves)
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MOV r7, r9, LSR #16
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ORR r7, r7, r12, LSL #16 @ r7 = dst14 | dst15<<16
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STMIA r0!,{r6,r7}
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BGT xLoop4
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ADD r0,r0,r2,LSL #1
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ADD r1,r1,r3
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SUBS r5,r5,#1
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BGT yLoop4
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ADD r13,r13,#256*4
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LDMFD r13!,{r4-r11,PC}
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