90 lines
2.0 KiB
C
90 lines
2.0 KiB
C
#include "common.h"
|
|
|
|
#include <util/atomic.h>
|
|
|
|
static int WriteRaw(word addr, byte data);
|
|
static byte ReadRaw(word addr);
|
|
|
|
int MEM_Read(mem_data_t *out)
|
|
{
|
|
// TODO
|
|
UNUSED(out);
|
|
UNUSED(ReadRaw);
|
|
return 0;
|
|
}
|
|
|
|
int MEM_Write(mem_data_t *in)
|
|
{
|
|
// TODO
|
|
UNUSED(in);
|
|
UNUSED(WriteRaw);
|
|
return 0;
|
|
}
|
|
|
|
static int WriteRaw(word addr, byte data)
|
|
{
|
|
// The EEMWE bit determines whether setting EEWE to
|
|
// one causes the EEPROM to be written. When EEMWE
|
|
// is set, setting EEWE within four clock cycles
|
|
// will write data to the EEPROM at the selected
|
|
// address.
|
|
|
|
// If EEMWE is zero, setting EEWE will have no
|
|
// effect. When EEMWE has been written to one by
|
|
// software, hardware clears the bit to zero after
|
|
// four clock cycles.
|
|
|
|
// Caution: An interrupt between the last two steps
|
|
// will make the write cycle fail, since the EEPROM
|
|
// Master Write Enable will time-out.
|
|
|
|
// If an interrupt routine accessing the EEPROM is
|
|
// interrupting another EEPROM Access, the EEAR or
|
|
// EEDR reGister will be modified, causing the
|
|
// interrupted EEPROM Access to fail.
|
|
|
|
// It is recommended to have the Global Interrupt
|
|
// Flag cleared during all the steps to avoid these
|
|
// problems.
|
|
|
|
// Wait until ready
|
|
while (EECR & BIT(EEWE));
|
|
|
|
// No interrupts during EEPROM write
|
|
ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
|
|
EEAR = addr;
|
|
EEDR = data;
|
|
|
|
// Write to address
|
|
EECR |= BIT(EEMWE);
|
|
EECR |= BIT(EEWE);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static byte ReadRaw(word addr)
|
|
{
|
|
// Wait until ready
|
|
while (EECR & BIT(EEWE));
|
|
|
|
EEAR = addr;
|
|
|
|
// The EEPROM Read Enable Signal EERE is the read
|
|
// strobe to the EEPROM. When the correct address
|
|
// is set up in the EEAR Register, the EERE bit
|
|
// must be written to a logic one to trigger the
|
|
// EEPROM read.
|
|
|
|
// Read from address
|
|
EECR |= BIT(EERE);
|
|
|
|
// The EEPROM read access takes one instruction,
|
|
// and the requested data is available immediately.
|
|
// When the EEPROM is read, the CPU is halted for
|
|
// four cycles before the next instruction is
|
|
// executed.
|
|
|
|
return EEDR;
|
|
}
|