Update module 'usart' to run on atmega1284p hardware

This commit is contained in:
2024-09-30 21:43:40 +02:00
parent 685a73e202
commit c3dc289d5f

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@@ -25,11 +25,11 @@ int USART_Init(void)
txhead = 0;
txtail = 0;
UCSRB = BIT(RXCIE); // Handle RXC interrupts
UCSRB |= BIT(RXEN) | BIT(TXEN); // Enable RX and TX circuitry
UCSRC = BIT(URSEL) | BIT(UCSZ0) | BIT(UCSZ1); // Using 8-bit chars
UBRRH = (USART_BAUD_PRESCALE >> 8); // Set baud rate upper byte
UBRRL = USART_BAUD_PRESCALE; // Set baud rate lower byte
UCSR0B = BIT(RXCIE0); // Handle RXC interrupts
UCSR0B |= BIT(RXEN0) | BIT(TXEN0); // Enable RX and TX circuitry
UCSR0C = BIT(USBS0) | BIT(UCSZ00) | BIT(UCSZ01); // 8-bit data, 2-bit stop
UBRR0H = (USART_BAUD_PRESCALE >> 8); // Set baud rate upper byte
UBRR0L = USART_BAUD_PRESCALE; // Set baud rate lower byte
return 0;
}
@@ -57,16 +57,16 @@ void USART_Putc(char ch)
txhead = head;
// Enable interrupt
UCSRB |= BIT(UDRIE);
UCSR0B |= BIT(UDRIE0);
}
// INT: Rx complete
ISR(USART_RXC_vect)
ISR(USART0_RX_vect)
{
short head;
byte data;
data = UDR; // Next byte ready
data = UDR0; // Next byte ready
// Wrap around if end of buffer reached
head = (rxhead + 1) & USART_RXBUF_MASK;
@@ -80,7 +80,7 @@ ISR(USART_RXC_vect)
}
// INT: Data register empty
ISR(USART_UDRE_vect)
ISR(USART0_UDRE_vect)
{
short tail;
@@ -88,10 +88,10 @@ ISR(USART_UDRE_vect)
if (txhead != txtail) {
// Write next byte to data register
tail = (txtail + 1) & USART_TXBUF_MASK;
UDR = txbuf[tail];
UDR0 = txbuf[tail];
txtail = tail;
} else {
// Disable interrupt
UCSRB &= ~BIT(UDRIE);
UCSR0B &= ~BIT(UDRIE0);
}
}