Reduce number of watchdog timer resets and rename Makefile target

Makefile

@@ -8,15 +8,6 @@
 # GENERAL SETTINGS
 # ==============================================================================
 
-# NOTE: System clock frequency should be a multiple of 1.8432MHz for USART.
-
-SRCDIR    := src
-BINDIR    := bin
-TMPDIR    := $(BINDIR)/build
-TARGET    := $(BINDIR)/core.hex
-ELFFILE   := $(BINDIR)/core.elf
-LOGFILE   := $(BINDIR)/core.log
-
 VERBOSE   := false
 #ARCH     := m1284p
 ARCH      := m32
@@ -32,6 +23,13 @@ AVD       := avrdude
 MKDIR     := mkdir -p
 RMR       := rm -rf
 
+SRCDIR    := src
+BINDIR    := bin
+TMPDIR    := $(BINDIR)/build
+TARGET    := $(BINDIR)/core.hex
+ELFFILE   := $(BINDIR)/core.elf
+LOGFILE   := $(BINDIR)/core.log
+
 CPPFLAGS  := -DF_CPU=$(FREQ) -I$(SRCDIR)
 CFLAGS    := -mmcu=$(MCU) -Os -std=c99 -Wall -Wextra -Werror
 OCFLAGS   := -j .text -j .data -O ihex
@@ -85,8 +83,8 @@ listen: ./opt/tools/serial-listen.py
 	$(E) "[PY3] $<"
 	$(Q) ./$<
 
-.PHONY: listen-web
-listen-web: ./opt/webgui/Makefile
+.PHONY: webgui
+webgui: ./opt/webgui/Makefile
 	$(E) "[MAK] $(<D)"
 	$(Q) $(MAKE) -sC $(<D)