Fix possible race condition and ensure proper reset flag detection

src/common/memory.c

@@ -192,6 +192,8 @@ static void WriteRaw(int addr, byte data)
 
 static byte ReadRaw(int addr)
 {
+	byte data;
+
 	// The EEPROM Read Enable Signal EERE is the read
 	// strobe to the EEPROM. When the correct address
 	// is set up in the EEAR Register, the EERE bit
@@ -214,7 +216,8 @@ static byte ReadRaw(int addr)
 
 		// Read from address
 		EECR |= BIT(EERE);
+		data = EEDR;
 	}
 
-	return EEDR;
+	return data;
 }

src/common/watchdog.c

@@ -75,7 +75,7 @@ bool WDT_HasTriggered(void)
 	// JTD  ISC2   –    JTRF  WDRF  BORF  EXTRF PORF 
 
 	// Is watchdog reset flag set?
-	isreset = ((MCUCSR & BIT(3)) == 1);
+	isreset = ((MCUCSR & BIT(WDRF)) != 0);
 
 	// XXX: Reset flag detection should be a separate
 	// module to handle the different types.