madcow/drybox-core
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Clear WDRF flag and set WDCE before enabling watchdog

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This commit is contained in:
Leon Krieg
2024-10-01 15:47:31 +02:00
parent 93590f7b75
commit 5a726f5d48
3 changed files with 21 additions and 19 deletions
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14
Makefile
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@@ -50,13 +50,8 @@ DEPENDS := $(FILES:%.c=$(TMPDIR)/%.d)
# AUXILIARY TARGETS (AND FUSE SETTINGS) # AUXILIARY TARGETS (AND FUSE SETTINGS)
# ============================================================================== # ==============================================================================
# .PHONY: all .PHONY: all
# all: flash all: flash
.PHONY: run
run: $(TARGET)
$(E) "[SIM] $<"
$(Q) $(SIM) -m $(MCU) -f $(FREQ) $<
.PHONY: flash .PHONY: flash
flash: $(TARGET) flash: $(TARGET)
@@ -69,6 +64,11 @@ flash: $(TARGET)
-U lock:w:0xFF:m \ -U lock:w:0xFF:m \
-U flash:w:$< -U flash:w:$<
.PHONY: run
run: $(TARGET)
$(E) "[SIM] $<"
$(Q) $(SIM) -m $(MCU) -f $(FREQ) $<
.PHONY: clean .PHONY: clean
clean: clean:
$(E) "[REM] $(TARGET)" $(E) "[REM] $(TARGET)"

18
src/common/watchdog.c
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@@ -36,8 +36,17 @@ void WDT_Enable(void)
// set. Once written to one, hardware will clear // set. Once written to one, hardware will clear
// WDCE after four clock cycles. // WDCE after four clock cycles.
// 00001111: Watchdog enabled, 2sec timeout // Setting WDCE before enabling the watchdog should
WDTCSR = BIT(WDE) | BIT(WDP2) | BIT(WDP1) | BIT(WDP0); // not be necessary according to the data sheet but
// it does not seem to work otherwise.
// Disable interrupts
ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
MCUSR &= ~BIT(WDRF);
WDTCSR = BIT(WDCE) | BIT(WDE);
// 00001111: Watchdog enabled, 2sec timeout
WDTCSR = BIT(WDE) | BIT(WDP2) | BIT(WDP1) | BIT(WDP0);
}
} }
void WDT_SetTimeoutFlag(byte flag) void WDT_SetTimeoutFlag(byte flag)
@@ -65,13 +74,13 @@ void WDT_SetTimeoutFlag(byte flag)
// Disable interrupts // Disable interrupts
ATOMIC_BLOCK(ATOMIC_RESTORESTATE) { ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
WDT_Reset();
WDTCSR = BIT(WDCE) | BIT(WDE); WDTCSR = BIT(WDCE) | BIT(WDE);
// Set new timer prescalar flag // Set new timer prescalar flag
WDTCSR = (WDTCSR & 0xC8) | flag; // C8=11001000 WDTCSR = BIT(WDE) | flag;
} }
} }
// XXX: COMMENTS UPDATED!
bool WDT_HasTriggered(void) bool WDT_HasTriggered(void)
{ {
bool isreset; bool isreset;
@@ -109,6 +118,7 @@ void WDT_Disable(void)
// Disable interrupts // Disable interrupts
ATOMIC_BLOCK(ATOMIC_RESTORESTATE) { ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
WDT_Reset();
WDTCSR = BIT(WDCE) | BIT(WDE); WDTCSR = BIT(WDCE) | BIT(WDE);
WDTCSR = 0; WDTCSR = 0;
} }

8
src/main.c
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@@ -57,14 +57,6 @@ static int Init(void)
Info("Initializing..."); Info("Initializing...");
// FIXME: Something is wrong here:
// - AVRDUDE sometimes fails to verify flash.
// - UART sometimes stops working.
// - External crystal problems?
// - Power supply problems?
// - Wrong fuses? Unlikely.
// - Bootloader problems?
// The watchdog timer is clocked from a separate // The watchdog timer is clocked from a separate
// on-chip oscillator which runs at 1 MHz. Eight // on-chip oscillator which runs at 1 MHz. Eight
// different clock cycle periods can be selected // different clock cycle periods can be selected